Exemplary embodiments of the present invention relate to a nonvolatile memory device and, more particularly, to a nonvolatile memory device capable of reducing the size of a pumping capacitor by reducing a load on a high voltage pump.
A nonvolatile memory device uses a plurality of operating voltages, such as a program voltage, a read voltage, an erase voltage, and a pass voltage, during a program operation, a read operation, and an erase operation.
Some of the operating voltages are much higher than an external power supply voltage and generated by raising the external power supply voltage using a pump circuit.
The pump circuit includes a pumping capacitor that occupies a large portion of the area of the pump circuit. The size of the pumping capacitor is determined by the amount of loads of circuits coupled to an output terminal. For example, the loads of the circuits coupled to the output terminal may include a load of global word lines, a load of local word lines, and a load of the junction capacitor of a pass transistor within a row decoder corresponding to each memory block.
FIG. 1 shows the construction of a conventional nonvolatile memory device.
The conventional nonvolatile memory device includes row decoders disposed on both sides of each of planes P0 and P1. In this construction, when one (for example, Block2) of a plurality of blocks within the plane P0 is selected, a high voltage is only to be supplied to local global word lines (for example, LGWL_P0L<65:0>) which are half of the local global word lines LGWL_P0L<65:0> and LGWL_P0R<65:0> corresponding to the plane P0. Accordingly, the output terminal of a high voltage generator 110 is coupled to row decoders which are half of the row decoders corresponding to the plane P0, so that load of the high voltage generator 110 is reduced.
As the degree of integration of nonvolatile memory devices is increased, a load of the high voltage generator 110 is increased. Accordingly, the size of a pumping capacitor forming the high voltage generator is increased.